It is common for a modern microprocessor chip (“chip”) to implement a cache system including a first cache level and a second cache level. The first cache level represents a small amount of very fast memory defined on the chip. The first cache level is used to provide a temporary holding place for data and instructions that have recently been transferred to or from a main memory that resides outside the chip. The second cache level is generally larger than the first cache level. The second cache level is defined between the first cache level and the main memory. Data access operations between the first cache level and the second cache level can be performed faster than between the first cache level and the main memory. Thus, the second cache level represents an intermediate memory that can quickly service requests from the first cache level.
In a multiprocessor chip, a single second cache level is often used to service multiple first cache levels corresponding to multiple processors. In general, the second cache level maintains a copy of the data in the first cache level of each processor. Thus, multiple first cache levels may store a common data item that is also stored in the second cache level. During operation of the cache system, it is important to maintain coherency between the first and second cache levels. This is particularly true when handling data errors identified within the first cache level. For example, if the first cache level modifies data stored therein due to identification of an error, the corresponding data in the second cache level needs to be modified in the same manner to remain consistent. Otherwise, a coherency problem may occur later.
Because the first cache level communicates directly with the processor, it is important to operate the first cache level in the most efficient manner possible. Therefore, a continuing need exists for advancements in cache system operation, particularly with respect to optimization of error handling in the first cache level while maintaining coherence with the second cache level.